Method of making integrated semiconductor structure having an MO

Details Method of making integrated semiconductor structure having an MO Method of making integrated semiconductor structure having an MO

1979-07-23

1981-09-22

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29577C, 29578, 148 15, 357 23, 357 59, B01J 1700, H01L 21265

Patent

active

042901863

ABSTRACT:
This disclosure is directed to an improved semiconductor capacitor structure especially useful in an integrated semiconductor structure with an MOS device and fabrication methods therefor. This semiconductor capacitor is particularly useful for forming the capacitor portion of a single MOS memory cell structure in a dynamic MOS random access memory which utilizes one MOS device in combination with a capacitor. In one specific disclosure embodiment, the semiconductor capacitor comprises a boron (P) implanted region in a substrate of P- type conductivity followed by a shallow arsenic (N) implant into the boron implanted region. The boron implanted region provides a P type conductivity which has a higher concentration of P type impurities than the concentration of impurities contained in the substrate which is of P- type conductivity. Thus, the boron implanted region performs the important function of preventing a surface N type inversion layer from being formed across the semiconductor surface beneath the silicon dioxide insulating layer which could occur across the substrate P- surface if the arsenic implant region was made into the P- substrate without the P type boron implant. The arsenic implant is of N type conductivity and has a higher concentration of impurities than the boron implant region. The dielectric portion of the semiconductor capacitor is the portion of the silicon dioxide layer located on the surface of the arsenic implanted region. A doped polysilicon electrode is formed over this portion of the silicon dioxide insulating layer and provides the other plate of the capacitor structure. In another embodiment that is disclosed, this above described semiconductor capacitor structure or device is combined with an MOS device in a single integrated semiconductor structure in order to provide a single MOS memory cell for dynamic random access memory chip utilizing the MOS device and the capacitor. Preferably, the semiconductor capacitor is shown as a connected extension of either the source or drain region of the MOS device.

REFERENCES:
patent: 3740731 (1973-06-01), Ohwada
patent: 3740732 (1973-06-01), Frandon
patent: 3891190 (1975-06-01), Vadasz
patent: 4125933 (1978-11-01), Baldwin
IEEE Transactions on Electron Devices, "Enhanced Capacitor for Due-Transistor Memory Cell", by Sodine & Kamins, 10/76, pp. 1187-1189.
IBM Tech. Disclosure Bulletin, "Vest. Diode-Cap, Memory Cells", by Chang et al., vol. 15, No. 9, Feb. 1973, p. 2887.

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