Method of making integrated MNOS and CMOS devices in a bulk sili

Details Method of making integrated MNOS and CMOS devices in a bulk sili Method of making integrated MNOS and CMOS devices in a bulk sili

1982-03-08

1984-06-19

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29577C, 29578, 148 15, 148187, 357 42, 357 91, H01L 2978, H01L 21265, B01J 1700

Patent

active

044546483

ABSTRACT:
This combination process enables both MNOS and CMOS devices to be fabricated upon the same wafer in very large scale integration systems. Conventional moat isolation techniques are replaced with low temperature ion implantation processing to accomplish substrate isolation. Both n and p channel MOS transistor diffusions and field oxidations are processed concurrently. Also, this process utilizes bulk silicon wafer material rather than epitaxial wafer material as the substrate.

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patent: 4315781 (1982-02-01), Henderson
patent: 4325180 (1982-04-01), Curran
patent: 4342149 (1982-08-01), Jacobs et al.
patent: 4373253 (1983-02-01), Khadder et al.

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