Method of making integrated CMOS and CTD by selective implantati

Details Method of making integrated CMOS and CTD by selective implantati Method of making integrated CMOS and CTD by selective implantati

1979-11-08

1982-02-09

Roy, Upendra

Metal treatment

Compositions

Heat treating

148187, 357 24, 357 42, 357 91, H01L 21263, H01L 754, H01L 2704

Patent

active

043148573

ABSTRACT:
A method of forming combination CMOS field effect transistors optionally with a charge transfer device in a single substrate. Different resistivities in the P type wells of the substrate are formed by a combination of masks; a high energy low dosage ion implantation of impurity passes through one mask but not the other, and a low energy high dosage ion implantation of the impurity is stopped by both masks. A significant number of fabrication steps is thus saved, and the devices so fabricated are threshold and field voltage compatible.

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patent: 4013484 (1977-03-01), Boleky et al.
patent: 4046606 (1977-09-01), Lambert
patent: 4052229 (1977-10-01), Pashley
patent: 4115796 (1978-09-01), Fujimoto et al.
patent: 4217149 (1980-08-01), Sawazaki

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