Fishing – trapping – and vermin destroying
Patent
1989-12-28
1991-06-25
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 41, 437192, 437228, 437235, 156643, H01L 2190
Patent
active
050266667
ABSTRACT:
An integrated circuit is made by a technique that provides a planar dielectric over gate, source, and drain regions without over-etching of the gate contact region, In the inventive process, the contact windows are etched in the conformal dielectric prior to the planarization step, so that the etch thickness is the same for the gate as for the source/drain windows. Then, a sacrificial planarizing polymer (e.g., a photoresist) is deposited to cover the conformal dielectric and fill the etched windows. Finally, a planarizing etch-back is performed, and the polymer is removed from the contact windows. A planarized dielectric is achieved without excessive etching of the gate windows.
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S. M. Sze editor, VLSI Technology, McGraw-Hill Book Co., New York (1983), pp. 107-108.
Hills Graham W.
Huttemann Robert D.
Olasupo Kolawole R.
AT&T Bell Laboratories
Fox James H.
Hearn Brian E.
Holtzman Laura M.
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