Method of making integrated circuits free from the formation of

Details Method of making integrated circuits free from the formation of Method of making integrated circuits free from the formation of

1975-09-02

1977-03-29

Ozaki, G.

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

148 335, 148189, 357 34, 357 48, H01L 2122

Patent

active

040147185

ABSTRACT:
In order to prevent the formation of a parasitic PNPN thyristor in an integrated circuit having at least one NPN transistor, a layer of semiconductor material of a conductivity type opposite that of the substrate is formed on the substrate. An isolation region of the same conductivity type as the substrate is formed on this layer and a further layer of the same conductivity type as the isolation region, but of a higher impurity concentration, is formed on the back surface of the substrate. A diffusion layer of the same conductivity type as the substrate, which serves as the base region of the NPN transistor, is formed on the layer having the conductivity type opposite to that of the substrate. A further layer of the same conductivity type and a higher impurity concentration than the isolation region is formed on the back surface of the substrate and an insolation layer is formed on the back surface of the substrate and on the substrate. A further diffusion layer of a conductivity type opposite to that of the substrate, which serves as the emitter region of the transistor is formed using the insolation layer as a mask.

REFERENCES:
patent: 3470036 (1969-09-01), Svedberg
patent: 3798079 (1974-03-01), Chu et al.
patent: 3916431 (1975-10-01), Khajezadeh

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