Method of making integrated circuit with reduced narrow-width ef

Details Method of making integrated circuit with reduced narrow-width ef Method of making integrated circuit with reduced narrow-width ef

1984-05-09

1986-02-11

Ozaki, George T.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29576W, 148 15, 148187, H01L 2182

Patent

active

045691177

ABSTRACT:
A method of making MOS integrated circuits employs high-pressure oxidation of the surface of a silicon slice to create thermal field oxide for device isolation. The implant used prior to this oxidation to provide the channel-stop regions beneath the field oxide may be at a lower dosage, and yet the field-transistor threshold voltage is maintained at a high level. Thus, encroachment of the channel stop impurity into the transistor channel is minimized, and higher density devices are permitted.

REFERENCES:
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patent: 4179792 (1979-12-01), Marshall et al.
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patent: 4271583 (1981-06-01), Kahng et al.
patent: 4361600 (1982-11-01), Brown
patent: 4370798 (1983-02-01), Lien et al.
patent: 4388121 (1983-06-01), Rao
patent: 4390393 (1983-06-01), Ghezzo et al.
patent: 4443933 (1984-04-01), DeBrebisson
patent: 4472874 (1984-09-01), Kurosawa et al.

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