Method of making integrated circuit with pair of MOS field effec

Details Method of making integrated circuit with pair of MOS field effec Method of making integrated circuit with pair of MOS field effec

1987-05-29

1988-09-20

Ozaki, George T.

Fishing, trapping, and vermin destroying

437 89, 437156, 437913, 437915, H01L 21425, H01L 21365

Patent

active

047725680

ABSTRACT:
The present invention is a method of making an integrated circuit device including a pair of MOSFETs each of which has a source or drain region which shares a common active region with the other. The method includes forming an epitaxial layer from nucleation sites, one of which is the source or drain region of the first MOSFET. The second MOSFET is then formed in the epitaxial layer so that one of the source or drain regions extends from one of the nucleation sites.

REFERENCES:
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patent: 4349394 (1982-09-01), Wei
patent: 4555843 (1985-12-01), Malhi
patent: 4603468 (1986-08-01), Lam
patent: 4628589 (1986-12-01), Sundaresan
patent: 4637127 (1987-01-01), Kurogi et al.
patent: 4651408 (1987-03-01), MacElwee et al.
patent: 4686758 (1987-08-01), Liu
patent: 4698316 (1987-10-01), Corboy, Jr. et al.

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