Method of making integrated circuit structure with narrow line w

Details Method of making integrated circuit structure with narrow line w Method of making integrated circuit structure with narrow line w

1993-05-21

1997-06-17

Niebling, John

Fishing, trapping, and vermin destroying

437184, H01L 2144, H01L 2148

Patent

active

056396880

ABSTRACT:
In a sub-micron line width process, a first layer of polysilicon 13 is patterned into lines 1,2 spaced a predetermined distance. An oxide layer 11 is deposited. A second layer of polysilicon 14 is deposited on the insulating layer. A gate contact 19 or emitter contact 35 is formed from the second polysilicon layer 14. The gate 19 or emitter 35 is spaced from the lines 1,2 a distance approximately equal to the thickness of the second polysilicon layer 14.

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patent: 5407532 (1995-04-01), Fang et al.
Wolf, "Silicon Procesing for the VLSI Era, vol. II", pp. 214-217, 1990.

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