Method of making high precision w-polycide-to-poly capacitors in

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437919, 437200, H01L 2170, H01L 2700

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active

055545580

ABSTRACT:
A method for making a polycide-to-polysilicon capacitor, which has a reduced IPO thickness and low voltage coefficient, is described. A first layer of doped polysilicon is formed over a silicon substrate. A silicide layer is formed over the first layer of doped polysilicon. The first layer of doped polysilicon and the silicide layer are patterned to form a polycide bottom plate of the capacitor. An oxide layer is formed over the bottom plate. The oxide layer is densified. A second layer of doped polysilicon is formed over the oxide layer. The second layer of polysilicon is patterned to form a top plate of the capacitor. The oxide layer is removed except under the top plate of the capacitor, where it acts as a capacitor dielectric, and, finally, the bottom plate is annealed.

REFERENCES:
patent: 4697330 (1987-10-01), Paterson et al.
patent: 4971924 (1990-11-01), Tigelaar et al.
patent: 5037772 (1991-08-01), McDonald
patent: 5338701 (1994-08-01), Hsu et al.

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