Method of making high coupling ratio DMOS electrically programma

Details Method of making high coupling ratio DMOS electrically programma Method of making high coupling ratio DMOS electrically programma

1979-11-13

1982-03-02

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 148 15, 148187, 357 23VT, 357 41, 365185, B01J 1700, H01L 2122, H01L 2126, G11C 1140

Patent

active

043172733

ABSTRACT:
An electrically programmable memory array of the floating gate type with a high coupling ratio is made by a DMOS process which allows the edges of the floating gates to be self-aligned with the edges of the control gates and produces improved characteristics in the form of higher gain and lower body effect. The source and drain regions are formed prior to applying the first level polysilicon by a process which leaves these regions covered with thick oxide, rather than using the polysilicon as a mask to define the gate areas. Double-diffused regions are formed on one or both sides of the channel, also beneath thick oxide, instead of using a P+ tank. The ratio of the capacitance between the floating gate and control gate to the total capacitance at the floating gate is increased and the degradation in the cell performance usually caused by the P+ tank is avoided.

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Ning et al., IBM-TDB, 21 (1978), 402.

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