Method of making hardened CMOS sub-micron field effect transisto

Details Method of making hardened CMOS sub-micron field effect transisto Method of making hardened CMOS sub-micron field effect transisto

1986-04-28

1987-09-22

Ozaki, George T.

Fishing, trapping, and vermin destroying

437 41, H01L 21385, H01L 21425

Patent

active

046945652

ABSTRACT:
The invention provides a novel high speed hardened CMOS structure and process for developing the structure. In a first embodiment, the <100> surface of the silicon wafer is preserved intact by building the field oxide above this surface so there is no transition from the <100> plane to the <111> plane. In a first embodiment, one of the gate electrode overlaps is avoided, thereby eliminating the sidewalk effect or parasitic device from causing leakage on that side of the channel. The preferred embodiment provides a device with no field oxide extending into the silicon wafer and with no overlap of the gate electrode over the field oxide. This is achieved by causing the gate metal interconnect to proceed linearly along the active region over either the source or drain before it leaves the active region, thereby avoiding the establishing of an extra field in the gate region. An alternative method for accomplishing the foregoing is to provide double metal layers and allow the gate metal interconnect to leave the active area directly from the gate electrode because the spacing is sufficient to render the metal interconnect field ineffective to cause parasitic problems; also, in this embodiment the metal interconnect can be run linearly along the active region and depart the same over the source or drain thereby even decreasing gate capacitance effects. A method for establishing sub-micron contacts is disclosed which permits manufacture of the CMOS devices to sub-micron dimensions.

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