Method of making flash memory with high coupling ratio

Details Method of making flash memory with high coupling ratio Method of making flash memory with high coupling ratio

1994-07-18

1995-06-27

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 52, 437228, 437984, 257321, H01L 21265

Patent

active

054279704

ABSTRACT:
A new method of fabricating a high coupling ratio Flash EEPROM memory cell is achieved. A layer of silicon dioxide is provided over the surface of a semiconductor substrate. A layer of silicon nitride is deposited over the silicon dioxide layer and patterned. The silicon dioxide layer not covered by the patterned silicon nitride layer is removed, thereby exposing portions of the substrate. A tunnel oxide layer is grown on the exposed portions of the semiconductor substrate. Silicon nitride spacers are formed on the sidewalls of the patterned silicon nitride layer. Ions are implanted into the substrate using the silicon nitride layer and spacers as a mask to form implanted regions within the semiconductor substrate. The semiconductor substrate is oxidized where the implanted regions have been formed leaving the thin tunnel oxide only under the silicon nitride spacers. The silicon nitride layer and spacers are removed. A first polysilicon layer is deposited over the surface of the silicon dioxide and tunnel oxide layers and patterned to form a floating gate. An interpoly dielectric layer is deposited over the patterned first polysilicon layer followed by a second polysilicon layer. The second polysilicon layer is patterned to form a control gate. Passivation and metallization complete the fabrication of the memory cell with improved coupling ratio.

REFERENCES:
patent: 5021848 (1991-06-01), Chiu
patent: 5155055 (1992-10-01), Gill et al.
patent: 5278089 (1994-01-01), Nakagawara
patent: 5310693 (1994-05-01), Hsue
"A Novel Sublithographic Tunnel Diode Based 5V-Only Flash Memory" by M. Gill et al, IEDM 90, .COPYRGT.1990 by IEEE pp. 119-122.
"A High Capacitive-Coupling Ratio (HiCR) Cell for 3V-Only 64 Mbit & Future Flash Memories", by Y. S. Hisamune et al, IEDM 93, .COPYRGT.1993 by IEEE, pp. 19-22.

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