Method of making flash EEPROM memory with reduced column leakage

Details Method of making flash EEPROM memory with reduced column leakage Method of making flash EEPROM memory with reduced column leakage

1995-03-14

1996-01-09

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 35, 437154, H01L 218247

Patent

active

054828813

ABSTRACT:
A flash EEPROM having reduced column leakage current suitably includes cells with more uniform erase times arranged in an array. An intermediate n+ implant immediately following the DDI implant step suitably provides an enhanced doping profile in the tunneling region, which increases the rate at which F-N tunneling occurs to erase the cells, and which increases the uniformity of F-N tunneling rates among memory cells within the array. A thermal cycle drives the intermediate n+ implant deeper into the tunneling region. Alternatively, an n+ implant may be performed at a relatively large angle with respect to the semiconductor substrate, which improves the doping concentration in the tunneling region of the source.

REFERENCES:
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 5100818 (1992-03-01), Arima et al.
patent: 5120671 (1992-06-01), Tang et al.
patent: 5335198 (1994-08-01), Van Buskirk et al.
patent: 5364806 (1994-11-01), Ma et al.

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