Method of making field effect transistors in an inner region of

Details Method of making field effect transistors in an inner region of Method of making field effect transistors in an inner region of

1990-03-21

1992-03-17

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437 47, 437 52, 437 89, 437915, H01L 2170

Patent

active

050968459

ABSTRACT:
A channel surface with a channel region and a gate electrode opposing to each other is formed approximately vertical to a main surface of a semiconductor substrate in the field effect transistor (FET). A p type (n type) single crystal silicon layer is formed in a hole of an insulating layer on the main surface of the substrate. N type (p type) drain and source regions are formed defining the channel region in the single crystal silicon layer. A gate electrode is formed above the channel region on the side wall of the single crystal silicon layer in the hole. The area of the main surface of the substrate occupied by one FET can be reduced in this manner. A semiconductor device can be provided in which FETs are integrated to a higher degree without degrading performance of the transistors. The method for manufacturing the semiconductor device comprises the steps of forming an insulating layer with a hole reaching to the main surface of the substrate, forming a single crystal silicon layer in the hole, forming a gate electrode on the side wall surface of the single crystal silicon layer, and forming source and drain regions in the single crystal silicon layer in selfalignment.

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