Method of making field effect transistor with T-shaped gate elec

Details Method of making field effect transistor with T-shaped gate elec Method of making field effect transistor with T-shaped gate elec

1994-09-23

1995-10-31

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 44, 437177, 437912, H01L 21266, H01L 218252, H01L 218232

Patent

active

054628849

ABSTRACT:
A semiconductor device with a small gate-source capacitance is fabricated by disposing a semiconductor epitaxial layer of one conductivity type on a substrate. Two metal layers which, when subjected to etching by a selected etchant, are etched at different rates, are disposed in a stack on the epitaxial layer. The stack is then subjected to dry-etching to form a gate electrode including a wider (larger gate length) upper electrode section and a narrower (smaller gate length) lower gate electrode section. The upper gate electrode section is used as a mask for implanting an impurity of the opposite conductivity type into the semiconductor epitaxial layer, which results in a source region having an edge close to but not extending into the portion beneath the lower gate electrode section.

REFERENCES:
patent: 4546540 (1985-10-01), Ueyanagi et al.
patent: 5115290 (1992-05-01), Murakami et al.
patent: 5272100 (1993-12-01), Satoh et al.
patent: 5344788 (1994-09-01), Noda
Ueda et al., "A New Vertical Double Diffused MOSFET--The Self-Aligned Terraced-Gate MOSFET", IEEE Transactions on Electron Devices, vol. ED-31, No. 4, Apr. 1984, pp. 416-420.
Ohta et al., "Quadruply Self-Aligned MOS (OSA MOS)--A New Short-Channel High-Speed High Density MOSFET For VLSI", IEEE Journal of Solid State Circuits, vol. SC-15, No. 4, Aug. 1980.
"Process For Making Very Small, Asymmetric, Field Effect Transistors", IBM Technical Disclosure Bulletin, vol. 30, No. 3, Aug. 1987, pp. 1136-1137.
Rodder et al., "Raised Source/Drain MOSFET With Dual Sidewall Spacers", IEEE Electron Device Letters, vol. 12, No. 3, Mar. 1991, pp. 88-91.
Suzuki et al., "A New Self-Aligned GaAs FET with A Mo/WSi T-Gate", IEEE Electron Device Letters, vol. EDL-6, No. 10, Oct. 1985, pp. 542-544.
Smith et al., "A 0.25 .mu.m Gate-Length Pseudomorphis HFET With 32-mW Output Power At 94 GHz", IEEE Electron Device Letters, vol. 10, No. 10, Oct. 1989, pp. 437-439.

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