Method of making field-effect semiconductor device on SOT

Details Method of making field-effect semiconductor device on SOT Method of making field-effect semiconductor device on SOT

1991-12-30

1993-07-06

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

148DIG150, 257347, 257354, H01L 21265, H01L 2186

Patent

active

052253562

ABSTRACT:
A field-effect semiconductor device of this invention includes a first insulating film formed on a semiconductor substrate, a source region of a second conductivity type and a drain region of the second conductivity type, which are arranged on the insulating film and are formed on both the sides of a semiconductor active layer of a first conductivity type, a second insulating film for covering the top and side surfaces of the semiconductor active layer, the source region, and the drain region, a gate electrode arranged on the second insulating film corresponding to the semiconductor active layer, a non-oxidizable third insulating film arranged on the second insulating film for covering the side surfaces of the semiconductor active layer and the source and drain regions, and the other regions, a fourth insulating film arranged on the non-oxidizable third insulating film, a fifth insulating film for covering a portion of the third insulating film located on the side surfaces of the source and drain regions, the fourth insulating film, the semiconductor active layer, the second insulating film arranged on the top surfaces of the source and drain regions, and a gate electrode arranged on the second insulating film, and a source electrode and a drain electrode arranged on the fifth insulating film and connected to the source region and the drain region, respectively, through contact holes formed in the fifth insulating film and the second insulating film.

REFERENCES:
patent: 4772927 (1988-09-01), Saito et al.
patent: 4809056 (1989-02-01), Shirato et al.
patent: 4965213 (1990-10-01), Blake
patent: 5047356 (1991-09-01), Li et al.
patent: 5073506 (1991-12-01), Marzara et al.
Y. Omura et al., "A 21.5 ps/Stage Ultra-Thin-Film CMOS/SIMOX at 2.5 V Using a 0.25-m Polysilicon Gate", 4th Symposium on SOI Technology & Devices, ESC, May 1990, Montreal, pp. 509-517.

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