Method of making FET containing stacked gates

Details Method of making FET containing stacked gates Method of making FET containing stacked gates

1977-12-23

1981-09-08

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

148187, 357 23, 357 59, 357 91, B01J 1700, H01L 2927

Patent

active

042882567

ABSTRACT:
A field effect transistor (FET) comprising a floating gate and a control gate in a stacked relationship with each other and being self-aligned with each other and self-aligned with respect to source and drain regions. The fabrication technique employed comprises delineating both the floating gate and control gate in the same lithographic masking step.

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patent: 4142926 (1979-03-01), Morgan
Scheibe et al., "Technology of . . . . SIMOS", IEEE-Trans. Electron Device, ED-24, May 1977, 600.

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