Method of making EPROM with separate erasing and programming reg

Details Method of making EPROM with separate erasing and programming reg Method of making EPROM with separate erasing and programming reg

1995-06-06

1996-10-15

Fourson, George

Fishing, trapping, and vermin destroying

437 52, 437193, H01L 218247

Patent

active

055653715

ABSTRACT:
An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (21). Each memory cell includes a source region (11) and a drain region (12) formed in a shared drain-column line (19), with a corresponding channel region in between. A Fowler-Nordheim tunnel-window (13a) is located opposite the channel over the source-column line (17) connected to source (11). A floating-gate conductor (13) includes a channel section (29) and a tunnel-window section (28). The floating-gate conductor is formed in two stages, the first stage forming the channel section (29) and the tunnel-window section (28) from a first-level polysilicon. This floating-gate channel section (29) is used as a self-alignment implant mask for the source (11) and drain (12) regions, such that the channel-junction edges are aligned with the corresponding edges of the channel section (29). A control-gate cenductor 14 is disposed over the floating-gate conductor (13), insulated by an intervening inter-level dielectric (26). The memory cell is programmed by hot-carrier injection from the channel to the floating-gate channel section (29), and erased by Fowler-Nordheim tunneling from the floating-gate tunnel-window section (28) through the tunnel window (13a). The program, erase and read regions of the cells are physically separate from each other, and the characteristics of each of those regions may be made optimum independently from each other.

REFERENCES:
patent: 5032533 (1991-07-01), Gill et al.
patent: 5045491 (1991-09-01), Gill et al.
patent: 5057446 (1991-10-01), Gill et al.
patent: 5371031 (1994-12-01), Gill et al.

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