Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating selected area
Reexamination Certificate
1999-07-06
2004-03-23
King, Roy (Department: 1742)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Coating selected area
C205S123000, C205S157000, C205S296000, C205S297000, C205S298000, C438S625000, C438S637000, C438S642000, C438S687000
Reexamination Certificate
active
06709562
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to interconnection wiring on electronic devices such as on integrated circuit (IC) chips and more particularly to void-free and seamless submicron structures fabricated by Cu electroplating from baths that contain additives conventionally used to produce bright, level, low-stress deposits.
BACKGROUND OF THE INVENTION
AlCu and its related alloys are a preferred alloy for forming interconnections on electronic devices such as integrated circuit chips. The amount of Cu in AlCu is typically in the range from 3 to 4 percent.
Replacement of AlCu by Cu and Cu alloys as a chip interconnection material results in advantages of performance. Performance is improved because the resistivity of Cu and certain copper alloys is less than the resistivity of AlCu; thus narrower lines can be used and higher wiring densities will be realized.
The advantages of Cu metallization have been recognized by the entire semiconductor industry. Copper metallization has been the subject of extensive research as documented by two entire issues of the Materials Research Society (MRS) Bulletin, one dedicated to academic research on this subject in MRS Bulletin, Volume XVIII, No. 6 (June 1993) and the other dedicated to industrial research in MRS Bulletin, Volume XIX, No. 8 (August 1994). A 1993 paper by Luther et al.,
Planar Copper-Polyimide Back End of the Line Interconnections for ULSI Devices
, in PROC. IEEE VLSI MULTILEVEL INTERCONNECTIONS CONF., Santa Clara, Calif., June 8-9, 1993, p. 15, describes the fabrication of Cu chip interconnections with four levels of metallization.
Processes such as Chemical Vapor Deposition (CVD) and electroless plating are popular methods for depositing Cu. Both methods of deposition normally produce at best conformal deposits and inevitably lead to defects (voids or seams) in wiring especially when trenches have a cross section narrower at the top than at the bottom as a result of lithographic or reactive ion etching (RIE) imperfections. Other problems of CVD have been described by Li et al.,
Copper-Based Metallization in ULSI Structures—Part II: Is Cu Ahead of its Time as an On-chip Material
?, MRS BULL., XIX, 15 (1994). In electroless plating, while offering the advantage of low cost, the evolution of hydrogen during metal deposition leads to blistering and other defects that are viewed as weaknesses for industry wide implementation.
An electroplating process for depositing copper, silver or gold onto a semiconductor wafer is described in U.S. Pat. No. 5,256,274 ('274), which issued on Oct. 26, 1993, to J. Poris. In FIG. 1A of '274, a copper conductor is shown with a seam in its center with the legend “GOOD” and in FIG. 1B a copper conductor is shown with a void in its center with the legend “BAD.” The plating bath contained 12 ounces/gallon of water of CuSO
4
, 5H
2
O, 10% by volume of concentrated sulfuric acid, 50 parts per millions of chloride ion from hydrochloric acid, and TECHNI-COPPER W additive 0.4% by volume provided by Technic Inc., P.O. Box 965, Providence, R.I. 02901. Plating was selectively deposited through an inert mask.
SUMMARY OF THE INVENTION
A process is described for fabricating a low cost, highly reliable Cu interconnect structure for wiring in integrated circuit chips with void-free seamless conductors of sub-micron dimensions. The process comprises deposition of an insulating material on a wafer, lithographically defining and forming sub-micron trenches or holes in the insulating material into which the conductor will be deposited to ultimately form lines or vias, depositing a thin conductive layer serving as a seed layer or plating base, depositing the conductor by electroplating from a bath containing additives and planarizing or chemical-mechanical polishing the resulting structure to accomplish electrical isolation of individual lines and/or vias.
The invention further provides a process for fabricating an interconnect structure on an electronic device comprising the steps of forming a seed layer on a substrate having insulating regions and conductive regions, forming a patterned resist layer on the seed layer, electroplating conductor material on the seed layer not covered by the patterned resist from a bath containing additives, and removing the patterned resist.
The invention further provides a process for fabricating an interconnect structure on an electronic device with void-free seamless conductors comprising the steps of forming an insulating material on a substrate, lithographically defining and forming lines and/or vias in which interconnection conductor material will be deposited, forming a conductive layer serving as a plating base, forming a patterned resist layer on the plating base, depositing the conductor material by electroplating from a bath containing additives, and removing the resist.
The invention further provides a process for fabricating an interconnect structure on an electronic device comprising the steps of forming a seed layer on a substrate having insulating regions and conductive regions, forming a blanket layer of conductor material on the seed layer from a bath containing additives, forming a patterned resist layer on the blanket layer, removing the conductor material where not covered by the patterned resist, and removing the patterned resist. The invention further provides a conductor for use in interconnections on an electronic device comprising Cu including small amounts of a material in the Cu selected from the group consisting of C (less than 2 weight percent), O (less than 1 weight percent), N (less than 1 weight percent), S (less than 1 weight percent), and Cl (less than 1 weight percent) formed by electroplating from a bath containing additives.
The interconnection material may be Cu electroplated from baths that contain additives conventionally used to produce bright, level, low-stress deposits. The rate of Cu electroplating from such baths is higher deep within cavities than elsewhere. This plating process thus exhibits unique superfilling properties and results in void-free seamless deposits that cannot be obtained by any other method. Interconnection structures made by Cu electroplated in this manner, are highly electromigration-resistant with an activation energy for electromigration equal to or greater than 1.0 eV. The conductor is composed substantially of Cu and small amounts of atoms and/or molecular fragments of C (less than 2 weight percent), C (less than 1 weight percent), N (less than 1 weight percent), S (less than 1 weight percent), and Cl (less than 1 weight percent).
Cu which is highly electromigration-resistant is electroplated from plating solutions that contain additives conventionally used to produce bright, ductile, and low-stress plated deposits.
It is an object of the present invention to electroplate conductors of Cu such as interconnect wiring without leaving a seam or a void in the center of the conductor.
It is a further object of the present invention to electroplate conductors of Cu with substantially uniform filling thickness where the conductors have a difference in widths such as less than 1 micron and greater than 10 microns. The depth to width ratio of a conductor may be equal to or greater than 1. The depth to width ratio of a via may exceed 1.
It is a further object of the present invention to lower the manufacturing cost of integrated circuits by the combined effects of 1) blanket deposition of Cu by electrolytic plating, 2) dual damascene fabrication (an approach in which two levels of metallization are fabricated in a single blanket-deposition step), and 3) the ability to planarize the upper surface by processes such as chemical mechanical polishing.
REFERENCES:
patent: 3328273 (1967-06-01), Creutz et al.
patent: 3652442 (1972-03-01), Powers et al.
patent: 3770598 (1973-11-01), Creutz
patent: 4110176 (1978-08-01), Creutz et al.
patent: 4339319 (1982-07-01), Aigo
patent: 4376685 (1983-03-01), Watson
patent: 4555315 (1985-11-01), Barbieri et al.
patent: 4975159 (1990-12-01), Dahms
patent: 5256274 (1993
Andricacos Panayotis Constantinou
Deligianni Hariklia
Dukovic John Owen
Edelstein Daniel Charles
Horkans Wilma Jean
King Roy
Leader William T.
Trepp Robert M.
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