Method of making electrically programmable and erasable memory d

Details Method of making electrically programmable and erasable memory d Method of making electrically programmable and erasable memory d

1994-05-06

1995-06-13

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 38, 437203, H01L 218247

Patent

active

054242339

ABSTRACT:
An improved structure and process of fabricating a programmable and erasable read only memory device wherein a thick oxide region is formed on the surface of a semiconductor substrate. The thick oxide region is removed forming a depression in the surface. Impurity ions are implanted into the depression forming a lightly doped source region. A tunnel oxide layer is formed on the substrate surface. Next, the floating gate layer is formed on the tunnel oxide layer which at least partially overlies the lightly doped source region. A gate insulation layer and control gate layer are formed over the floating gate layer. Subsequently, the source and drain regions are formed in the substrate on opposite sides of the gate structure. A dielectric layer is formed over the control gate region and substrate. Contact opening are formed. Electrical contacts and metallurgy lines with appropriate passivation are formed that connect the source, drain and control gate to form an electrical programmable memory device.

REFERENCES:
patent: 4997777 (1991-03-01), Boivin
patent: 5049515 (1991-09-01), Tzeng
patent: 5108937 (1992-04-01), Tsai et al.
"Optimization of a Source-Side-Injection FAMOS Cell for Flash EPROM Applications", David K. Y. Lui et al, IEDM Tech Dig., (no month) 1991 pp. 315-318.

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