Method of making electrically erasable and electrically programm

Details Method of making electrically erasable and electrically programm Method of making electrically erasable and electrically programm

1991-12-30

1993-03-02

Thomas, Tom

Fishing, trapping, and vermin destroying

437 34, 437 48, 437 52, 437228, 437229, H01L 2170

Patent

active

051908875

ABSTRACT:
A method of forming a doped region within a monocrystalline silicon layer of an integrated circuit having an electrically erasable and electrically programmable memory device on a semiconductor substrate, wherein the doped region lies within a channel region near a drain region, but does not lie within a source region. After a patterned layer is formed over the channel region, the substrate is doped by ion implantation with a first dopant at a tilt angle no less than a minimum tilt angle and at about a predetermined azimuthal angle, such that a significant number of ions enter a drain region and a channel region near the drain region and substantially no ions enter a source region. The first dopant is the same dopant type as the monocrystalline silicon layer dopant. The drain region is masked. The source region is doped with a second dopant. The second dopant is an opposite dopant type as the monocrystalline silicon layer dopant. The source region and the drain region are doped with a third dopant. The third dopant is the same dopant type as the second dopant. The third dopant dose is heavier than the first dopant dose, and the second dopant diffusion coefficient is greater than the third dopant diffusion coefficient.

REFERENCES:
patent: 4232439 (1980-11-01), Shibata
patent: 4642881 (1987-02-01), Matsakawa et al.
patent: 4698787 (1987-10-01), Mukherjee
patent: 4780424 (1988-10-01), Holler
Tam, et al., "A High Density CMOS 1-T Electrically Erasable Non-Volatile (Flash) Memory Technology," Symposium on VLSI Technology, pp. 31-32 (1988).
Gill, et al., "A 5-Volt Contactless Array 256KBit Flash EEPROM Technology," IEDM, pp. 428-431 (1988).
Masuoka, et al., "A New Flash E.sup.2 PROM Cell Using Triple Polysilicon Technology," IEDM, pp. 464-467 (1984).
U.S. patent application Ser. No. 07/700,512, filed May 15, 1991.
Kume, et al., "A Flash-Erase EEPROM Cell with an Asymmetric Source and Drain Structure," IEDM, pp. 560-563 (1987).
Ohshima, et al., "Process and Device Technologies for 16Mbit EPROMs with Large-Tilt-Angle Implanted P-Pocket Cell," IEDM, pp. 95-98 (1990).

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