Method of making electrically conductive regions in monolithic s

Details Method of making electrically conductive regions in monolithic s Method of making electrically conductive regions in monolithic s

1983-02-04

1987-09-08

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

148DIG46, 148DIG93, 357 24, 437188, 437 51, H01L 2144

Patent

active

046914340

ABSTRACT:
In the manufacture of semi-custom integrated circuits silicon wafers with P and N or N and P structures are used, and interconnections to establish a specific application must be created. Unlike currently known technologies, electrically conductive film with standardized openings made according to a pre-arranged raster must be deposited on the silicon wafer. Subsequently the conductive film, will be removed from between the openings directly or indirectly by means of electromagnetic radiation in order to produce the required circuit configuration. A laser beam is particularly appropriate for this since it can be positioned and controlled, and can be used directly for the exposure of a photosensitive film. The creation of insular conductive film is then achieved through a photo- etch technique. By use of this process, an expensive customer specific photo mask can be avoided. A semiconductor device manufactured according to this process exhibits in its conductive film a regular arrangement of openings which are able to form the ends, sides or corners of insular conductive film.

REFERENCES:
patent: 4037075 (1977-07-01), Pugsley et al.
patent: 4181563 (1980-01-01), Miyaka et al.
patent: 4193687 (1980-03-01), Reekstin et al.
patent: 4207585 (1980-06-01), Rao
patent: 4231149 (1980-11-01), Chapman et al.
patent: 4243866 (1981-01-01), Pfeiffer et al.
patent: 4301191 (1981-11-01), Peek
patent: 4352005 (1982-09-01), Evans et al.
patent: 4400797 (1983-08-01), Iwanami
patent: 4493666 (1985-01-01), Nonomura et al.
Percival et al., "Designing a Laser-Personalized Gate Array", VLSI Design, Feb. 1984, pp. 54-61.
Colclaser, Microelectronics: Processing and Device Design, John Wiley & Sons, New York, 1980, pp. 22-52 and 101-116.
Bhagat et al., "Contact Hole Formation in IC Using Ion Beam Nitriding", J. Electro. Chem. Soc., vol. 130, No. 11, Nov. 83.
Bhattacharyya et al., "Generators of Vias in Polyimide by Rapid Heating and Controlled Evaporation of the Underlying Metallurgy W/Palsed Laser", IBM Tech. Discl. Bul., vol. 24, No. 11A, Apr. 82.

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