Method of making EEPROM flash memory cell with erase gate

Details Method of making EEPROM flash memory cell with erase gate Method of making EEPROM flash memory cell with erase gate

1994-10-28

1997-07-01

Niebling, John

Fishing, trapping, and vermin destroying

437 48, 257320, H01L 21265, H01L 218247

Patent

active

056438125

ABSTRACT:
An EEPROM flash memory cell and a process for formation thereof are disclosed. The EEPROM flash memory cell includes: a source; a drain; a gate insulating layer disposed upon a channel between the source and the drain; a floating gate electrode disposed upon the gate insulating layer and facing toward the channel; and a control gate electrode disposed upon the floating gate electrode across an intermediate insulating layer; and further includes, an erasing electrode for contacting with at least one side of the floating gate electrode at least at one or more spots thereof across a tunneling insulating layer.

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Virgil Niles Kynett, et al.,; "A 90-ns One-Million Erase/Program Cycle 1-Mbit Flash Memory"; IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989; pp. 1259-1263.
Hitoshi Kume et al.; "A 3.42 .mu.m.sup.2 Flash Memory Cell Technology Conformable to a Sector Erase"; 8B-3; pp. 77-78, no date provided.
N. Kodama, et al.; "A 5Y Only 16 Mbit Flash EEPROM Cell Using Highly Reliable Write/Erase Technologies"; 8B-2; pp. 75-76, no date.
Sameer Haddad, et al.; "Degradations Due to Hole Trapping in Flash Memory Cells"; IEEE Electron Device Letters, vol. 10, No. 3, Mar. 1989, pp. 117-119.
T.C. Ong, et al.; "Erratic Erase in Etox.TM. Flash Memory Array"; 7A-2; pp. 83-84, no date provided.
N. Ajika, et al.; "A 5 Volt Only 16M Bit Flash EEPROM Cell With a Simple Stacked Gate Structure"; IEDM-115; pp. 5.7.1-5.7.4, 1990.

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