Method of making EEPROM array with buried N+ windows and with se

Details Method of making EEPROM array with buried N+ windows and with se Method of making EEPROM array with buried N+ windows and with se

1993-07-09

1994-12-06

Thomas, Tom

Fishing, trapping, and vermin destroying

437 43, 437 48, H01L 2170

Patent

active

053710312

ABSTRACT:
An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source region (11) and a drain region (12), with a corresponding channel region between. A Fowler-Nordheim tunnel-window (13a) is located over the source line (17) connected to source (11). The source line (17) consists of alternating buried N+ windows (17a) and source regions (11). A floating gate (13) includes a tunnel-window section. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the source (11) and drain (12) regions, such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch). The memory cell is programmed by hot-carrier injection from the channel to the floating gate (13), and erased by Fowler-Nordheim tunneling from the floating gate (13) through the tunnel window (13a) to the source-line (17). The program and erase regions of the cells are physically separate from each other, and the characteristics, including the oxides, of each of those regions may be made optimum independently from each other.

REFERENCES:
patent: 4451904 (1984-05-01), Sugiura et al.
patent: 4668970 (1987-05-01), Yatsuda et al.
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 5008721 (1991-04-01), Gill et al.
patent: 5019527 (1991-05-01), Ohshima
patent: 5081056 (1992-01-01), Mazzali et al.
patent: 5215934 (1993-06-01), Tzeng

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