Method of making DRAM having a stacked capacitor

Details Method of making DRAM having a stacked capacitor Method of making DRAM having a stacked capacitor

1991-10-23

1993-12-07

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437919, H01L 2170

Patent

active

052683222

ABSTRACT:
A DRAM comprising a silicon substrate with a field oxide layer 2, gate oxide layer 3, gate electrode and gate electrode lines 4A, 4B, oxide spacers 5 and drain and source electrodes on the silicon substrate 1 to define a MOSFET 25 is disclosed. A first insulating layer 7 covers the MOSFET 25 except for a portion of said source electrode 6B. A charge storage electrode 11A, with at least one tunnel space 9B having walls formed therein, overlies the source electrode 6B and is in electrical contact with the source electrode 6B. A capacitive dielectric layer 13 covers the charge storage electrode 11A and the walls 9C of each the tunnel space 9B. A plate electrode 14A is formed on the capacitive dielectric layer 13 and covers the charge storage electrode 11A and on the walls of each tunnel space 9B to define a stack capacitor having an increased area for the charge storage electrode 11A which results in an increased capacitance of the stack capacitor. A third insulating layer 15 covers at least the plate electrode 14A, except for a portion of the drain electrode 6A; and a bit line electrode 17 formed on the third insulating layer 15 is electrically connected to the drain of the MOSFET. A method of manufacturing the DRAM having at least one tunnel plate electrode is also disclosed.

REFERENCES:
patent: 5049957 (1991-09-01), Inoue et al.
patent: 5068698 (1991-11-01), Koyama
patent: 5071781 (1991-12-01), Seo et al.
patent: 5102820 (1992-04-01), Chiba
patent: 5164337 (1992-11-01), Ogawa et al.

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