Method of making dram cell with stacked capacitor

Details Method of making dram cell with stacked capacitor Method of making dram cell with stacked capacitor

1989-10-27

1991-10-29

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 47, 437 60, 437191, 437193, 437228, 437919, H01L 27108

Patent

active

050616510

ABSTRACT:
In a semiconductor memory integrated circuit device having a stacked capacitor cell, a first plate electrode and a first dielectric film are formed underneath a charge storage electrode a charge storage electrode, and a second dielectric film and a second plate electrode are formed over the charge storage electrode. The charge storage electrode has contact with the diffusion region through a contact hole penetrating the first dielectric material. The first and second plate electrodes are connected via a contact hole penetrating the first and second electric films outside the cell area. Because both the upper surface and the lower surface of the charge storage electrode are utilized for formation of the capacitor the size of the capacitor can be halved to produce the same capacitance.

REFERENCES:
Ohta et al., "Quadruply Self-Aligned Stacked High-Capacitance RAM Using Ta.sub.2 O.sub.5 High-Density ULSI Dynamic Memory" IEEE Trans. on Electrons Devices, vol. ED-29, No. 3, Mar. 1982, pp. 368-376.

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