Method of making cmos with shallow source and drain junctions

Details Method of making cmos with shallow source and drain junctions Method of making cmos with shallow source and drain junctions

1989-01-24

1990-07-31

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437 34, 437 57, 437162, 437192, 437200, 437 46, 437950, 357 44, 357 59, 148DIG35, 148DIG123, H01L 21235

Patent

active

049450700

ABSTRACT:
A CMOS device having shallow source and drain regions is formed in a body of single crystalline silicon having a major surface by forming in the body adjacent well regions of opposite conductivity type having an isolation region of an insulating material extending into the body from the major surface along the junction of the well regions. Thin layers of silicon oxide are formed on the major surface over each of the well regions, and a gate line of conductive polycrystalline silicon is formed over each of the silicon oxide layers. The side walls of the gate lines are covered with a layer of silicon oxide. A layer of polycrystalline silicon is selectively deposited on the surface of the body at each side of each gate line and on the gate lines. A layer of a refractory metal is deposited on the polycrystalline silicon layer. The polycrystalline silicon layer is heated to cause the metal to react with the silicon and form a metal silicide region at least partially through the polycrystalline silicon layer. The silicide region over each of the well regions is doped with a conductivity modifier of a conductivity type opposite that of the well region. The device is then heated to diffuse the conductivity modifiers through the polycrystalline silicon layer into the silicon body to form shallow source and drain regions in each well at each side of the gate lines.

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