Method of making CMOS structure with retarded electric field for

Details Method of making CMOS structure with retarded electric field for Method of making CMOS structure with retarded electric field for

1977-10-17

1979-07-17

Rutledge, L. Dewayne

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

29571, 148187, 148191, 357 23, 357 41, 357 42, H01L 21225, H01L 2174

Patent

active

041614178

ABSTRACT:
Method for making CMOS device utilizing a retarded electric field for reducing the current gain in the base region of parasitic transistors in the device. A buried layer is utilized in the base region of the parasitic transistor, and the resistivities of the buried layer and substrate are chosen to reduce both NPN and PNP betas and also to reduce the distributed resistance shunting the P+N and N+P junctions, thereby increasing the level of current required to produce latch-up in the device.

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patent: 3447046 (1969-05-01), Cricchi et al.
patent: 3748545 (1973-07-01), Beale
patent: 3920481 (1975-11-01), Hu
patent: 3971059 (1976-07-01), Dunkley et al.
patent: 4032372 (1977-06-01), Vora
Antipov, I. "Forming Complementary Field-Effect . . . and NPN Transistors" I.B.M. Tech. Discl. Bull., vol. 16, No. 8, Jan. 1974, pp. 2701-2703.
Chang et al., "Complementary Bipolar Device Structure" Ibid., vol. 17, No. 1, Jun. 1974, pp. 21-22.
Ma et al., "Forming Bipolar and Complementary FET . . ." Ibid., vol. 16, No. 7, Dec. 1973, pp. 2287-2288.

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