Method of making CMOS integrated circuit device

Details Method of making CMOS integrated circuit device Method of making CMOS integrated circuit device

1979-10-03

1981-10-20

Roy, Upendra

Metal treatment

Compositions

Heat treating

148187, 357 23, 357 42, 357 91, H01L 2122, H01L 2978

Patent

active

042958970

ABSTRACT:
An improved CMOS device and method of making it are provided which utilize basically the standard N-channel self-aligned silicon gate structure and process, modified to include a P-channel transistor. A P-type substrate is used as the starting material, with an N-type tank formed for the P-channel transistor. Field oxide is grown after the N-type tank is formed. A polycrystalline silicon layer is deposited and patterned to create gates for both N- and P-channel transistors, then separately masked P- and N-type diffusions or implants form the sources and drains for the two types of transistors.

REFERENCES:
patent: 4013484 (1977-03-01), Boleky et al.
patent: 4045250 (1977-08-01), Dingwall
patent: 4135955 (1979-01-01), Gasner et al.
patent: 4139402 (1979-02-01), Steinmaier et al.
patent: 4205342 (1980-05-01), Darwish et al.
patent: 4210465 (1980-07-01), Brower
patent: 4217149 (1980-08-01), Sawazaki
Chang et al., IBM-TDB, vol. 16, (1973) 1635.

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