Method of making CMOS device and contacts therein by enhanced ox

Details Method of making CMOS device and contacts therein by enhanced ox Method of making CMOS device and contacts therein by enhanced ox

1982-09-03

1984-09-11

Roy, Upendra

Metal treatment

Compositions

Heat treating

29571, 29576B, 29578, 148187, 357 42, 357 91, H01L 21225, H01L 21265, B01J 1700

Patent

active

044708521

ABSTRACT:
A CMOS process utilizes preferential oxidation of arsenic-doped regions and the reduced diffusivity of boron in arsenic-doped regions to eliminate photomask steps and to form self-aligned enhanced p.sup.+ and n.sup.+ contacts.

REFERENCES:
patent: 3886004 (1975-05-01), Bruchez
patent: 4170492 (1979-10-01), Bartlett et al.
patent: 4265685 (1981-05-01), Seki
patent: 4329773 (1982-05-01), Geipel, Jr. et al.
patent: 4385947 (1983-05-01), Halfacre et al.
patent: 4391650 (1983-07-01), Pfeifer et al.
Nomura et al., in Ion Implantation in S/C, Ed. Namba, Plenum, 1975, N.Y. p. 681.
"Polysilicon Oxidation Self-Aligned MOS (POSA MOS)--A New Self-Aligned Double Source/Drain Ion Implantation Technique for VLSI" by S. Hsia et al., IEEE Electron Device Letters, vol. EDL 3, No. 2, Feb. 1982, pp. 40-42.
"A New Self-Aligned Contact Technology" by Mitsuru Sakamoto et al., IC Division, Nippon Electric Company, Ltd., Sagamihara, Japan 1980 IEEE, pp. 136-139.
"High-Performance Transistors with Arsenic-Implanted Polysil Emitters" by Jurgen Graul et al., IEEE Journal of Solid-State Circuits, vol. SC-11, No. 4, Aug. 1976, pp. 491-495.
"Al/Poly-Si Metallization for Small Geometry, Shallow Junction Contacts and Fine Line Interconnects" by S. Vaidya, Bell Telephone Laboratories, ECS, p. 369.
"Electromigration in Aluminum/Poly-Silicon Composites" by S. Vaidya, Bell Laboratories, Appl. Phys. Lett. 39(11), 1981 American Institute of Physics, pp. 900-902.
"A New Type of Device Structure for Bipolar Logic IC's with Polysilicon Emitter Regions (PER)" by Jiang Xiangliu, Beijing Semiconductor Device Research Institute, Beijing, The People's Republic of China, 2 pages.
"Experimental Results on Submicron-Size p-Channel MOSFET's" by W. Fichtner, et al., IEEE Electron Device Letters, vol. EDL-3, No. 2, Feb. 1982, pp. 34-37.
"Oxidation Kinetics of As-Doped Polysilicon in a Steam Environment" by L., Baldi, et al., ECS Meeting, St. Louis, May 1980, 18 pages.
"Considerations for Scaled CMOS Source/Drains" by D. B. Scott, et al., Texas Instruments Incorporated, Central Research Laboratories, IEDM 81, IEEE 1981.
C. P. Ho, "Silicon Oxide Studies: Physical Modeling and Device Applications of Thermal Oxidation of Heavily Doped Silicon", Stanford Electronics Laboratories, Technical Report No. 4970-2, Nov. 1978.

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