Method of making CMOS device allowing three-level interconnects

Details Method of making CMOS device allowing three-level interconnects Method of making CMOS device allowing three-level interconnects

1979-10-11

1982-04-20

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 148 15, 148187, 357 42, 357 65, 357 91, H01L 21225, B01J 1700

Patent

active

043251692

ABSTRACT:
An improved CMOS device and method of making it are provided which utilize basically the standard N-channel self-aligned silicon gate structure and process (with implants for self-alignment), modified to include P-channel transistors and to allow three levels of interconnects. A P-type substrate is used as the starting material, with an N-type tank formed for the P-channel transistor. The source and drain regions, N+ or P+, are defined prior to the polycrystalline silicon gate; thus the source and drain may run under polysilicon. Self-aligning implants after the polysilicon is defined produce the advantages of self-aligned gates.

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