Method of making chalogenide memory device

Details Method of making chalogenide memory device Method of making chalogenide memory device

1996-07-22

1998-08-04

Niebling, John

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Responsive to electromagnetic radiation

438102, H01L 2100

Patent

active

057892776

ABSTRACT:
A method for fabricating chalcogenide memories in which ultra-small pores are formed in insulative layers using disposable spacers. The chalcogenide memory elements are positioned within the ultra-small pores. The chalcogenide memory elements thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms.

REFERENCES:
patent: 3423646 (1969-01-01), Cubert et al.
patent: 3796926 (1974-03-01), Cole et al.
patent: 4099260 (1978-07-01), Lynes et al.
patent: 4115872 (1978-09-01), Bluhm
patent: 4174521 (1979-11-01), Neale
patent: 4194283 (1980-03-01), Hoffmann
patent: 4203123 (1980-05-01), Shanks
patent: 4227297 (1980-10-01), Angerstein
patent: 4272562 (1981-06-01), Wood
patent: 4458260 (1984-07-01), McIntyre et al.
patent: 4502208 (1985-03-01), McPherson
patent: 4569698 (1986-02-01), Feist
patent: 4757359 (1988-07-01), Chiao et al.
patent: 4804490 (1989-02-01), Pryor et al.
patent: 4809044 (1989-02-01), Pryor et al.
patent: 4823181 (1989-04-01), Mohsen et al.
patent: 4876220 (1989-10-01), Mohsen et al.
patent: 4876668 (1989-10-01), Thakoor et al.
patent: 4881114 (1989-11-01), Mohsen et al.
patent: 4892840 (1990-01-01), Esquivel et al.
patent: 5144404 (1992-09-01), Iranmanesh et al.
patent: 5166096 (1992-11-01), Cote et al.
patent: 5166758 (1992-11-01), Ovshinsky et al.
patent: 5177567 (1993-01-01), Klersy et al.
patent: 5296716 (1994-03-01), Ovshinsky et al.
patent: 5335219 (1994-08-01), Ovshinsky et al.
patent: 5341328 (1994-08-01), Ovshinsky et al.
patent: 5359205 (1994-10-01), Ovshinsky
patent: 5363329 (1994-11-01), Troyan
patent: 5510629 (1996-04-01), Karpovich et al.
patent: 5536947 (1996-07-01), Klersy et al.
Kim and Kim, "Effects of High-Current Pulses on Polycrystalline Silicon Diode with n-type Region Heavily Doped with Both Boron and Phosphorus," J. Appl. Phys., 53(7):5359-5360, 1982.
Neale and Aseltine, "The Application of Amorphous Materials to Computer Memories," IEEE, 20(2):195-205, 1973.
Pein and Plummer, "Performance of the 3-D Sidewall Flash EPROM Cell," IEEE, 11-14, 1993.
Post and Ashburn, "Investigation of Boron Diffusion in Polysilicon and its Application to the Design of p-n-p Polysilicon Emitter Bipolar Transistors with Shallow Emitter Junctions," IEEE, 38(11):2442-2451, 1991.
Post et al., "Polysilicon Emitters for Bipolar Transistors: A Review and Re-Evaluation of Theory and Experiment," IEEE, 39(7):1717-1731, 1992.
Post and Ashburn, "The Use of an Interface Anneal to Control the Base Current and Emitter Resistance of p-n-p Polysilicon Emitter Bipolar Transistors," IEEE, 13(8):408-410, 1992.
Rose et al., "Amorphous Silicon Analogue Memory Devices," J. Non-Crystalline Solids, 115:168-170, 1989.
Schaber et al., "Laser Annealing Study of the Grain Size Effect in Polycrystalline Silicon Schottky Diodes," J. Appl. Phys., 53(12):8827-8834, 1982.
Yamamoto et al., "The I-V Characteristics of Polycrystalline Silicon Diodes and the Energy Distribution of Traps in Grain Boundaries," Electronics and Communications in Japan, Part 2, 75(7):51-58, 1992.
Yeh et al., "Investigation of Thermal Coefficient for Polycrystalline Silicon Thermal Sensor Diode," Jpn. J. Appl. Phys., 31(Part 1, No. 2A):151-155, 1992.
Oakley et al., "Pillars--The Way to Two Micron Pitch Multilevel Metallisation," IEEE, 23-29, 1984.

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