Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Including isolation structure
Reexamination Certificate
2000-06-20
2002-05-28
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Including isolation structure
C438S322000, C438S325000
Reexamination Certificate
active
06395610
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductors, and, more particularly, to bipolar transistors and associated manufacturing methods.
BACKGROUND OF THE INVENTION
Semiconductor devices in the form of integrated circuits are widely used in most electronic devices. For example, computers, cellular telephones, and other similar devices typically include one or more integrated circuits (ICs). In addition, many typical types of ICs are based upon metal-oxide semiconductor (MOS) technology wherein each transistor includes doped regions in a semiconductor substrate.
A bipolar transistor or bipolar junction transistor (BJT) is a semiconductor device commonly used for amplification. The device can amplify analog or digital signals. It can also function as an oscillator. Physically, a bipolar transistor amplifies current, but it can be connected in circuits designed to amplify voltage or power. Bipolar transistors are formed from the junction of three pieces of doped silicon called the emitter, collector and base. There are two major types of bipolar transistors, called PNP and NPN. A PNP transistor has a layer of N-type semiconductor between two layers of P-type material. An NPN transistor has a layer of P-type material between two layers of N-type material. In P-type material, electric charges are carried mainly in the form of electron deficiencies called holes. In N-type material, the charge carriers are primarily electrons.
The bipolar transistor has advantages and disadvantages relative to the FET (field-effect transistor). Bipolar devices can switch signals at high speeds, and can be manufactured to handle large currents so that they can serve as high-power amplifiers in audio equipment and in wireless transmitters. Bipolar devices are not especially effective for weak-signal amplification, or for applications requiring high circuit impedance. A single IC can contain many thousands of bipolar transistors, along with other components such as resistors, capacitors, and diodes.
More specifically, a typical bipolar transistor includes a thin insulating layer of silicon oxide formed over the emitter, base and collector regions to separate the respective contacts or electrodes. The contacts may be a metal or doped polysilicon layer, for example.
As device dimensions have been reduced in semiconductor processing, the quality of this oxide layer has become even more important. A preferred approach to forming the oxide may be by thermal oxidation. The thermally grown oxide provides good electrical performance, provides good mechanical bonding to the underlying silicon substrate portion, and helps to block unwanted ion implantation and diffusion of dopants into the substrate.
U.S. Pat. No. 5,869,405 to Gonzalez et al. discloses in situ rapid thermal etching and oxidation to form an oxide. In particular, an oxidation step is followed by an etch step to remove contamination and damage from the substrate. Repeated in situ oxidation and etch steps may be used until a desired removal of contamination or silicon damage is achieved.
U.S. Pat. No. 5,81,892 to Lojek et al. discloses a method for making an oxide including both pre- and post-oxidation anneal steps. The patent provides that the anneals, the ambients selected, and various cleaning steps help ensure a high quality oxide. A portion of the oxide layer grown during the high temperature (1000° C.) anneal and subsequent cool down is desirably reduced to less than about 20 Å, and its growth is the necessary byproduct of incorporating oxygen into the oxide bulk for the benefit of improving electrical performance.
As device dimensions scale down rapidly with the advance of manufacturing technologies, the electric field in the thin oxides continues to increase. Part of the consequence of such increased electric field and the thinning of the oxides is the increased trap generation at the oxide interface or within the thin oxides. The trap generation and the capture of channel electrons by the traps in turn leads to increased low frequency noise and transconductance degradation. Additionally, the emitter-base breakdown voltage may result in hot carrier aging (HCA) of the adjacent oxide and thus affect the gain of the device.
Unfortunately, despite continuing efforts and developments in the area of forming high quality oxides, device performance and longer term reliability is still compromised by conventional oxides, especially as device dimensions continue to be reduced.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is therefore an object of the present invention to provide a bipolar transistor semiconductor device including a high quality oxide layer and a method for making the device.
This and other objects, features and advantages in accordance with the present invention are provided by a method of making a bipolar transistor including forming respective emitter, base and collector regions in a silicon substrate, and forming an oxide layer adjacent the silicon substrate. The oxide layer is formed by growing a first oxide portion by upwardly ramping the silicon substrate to a first temperature lower than a glass transition temperature, and exposing the silicon substrate to an oxidizing ambient at the first temperature and for a first time period, and growing a second oxide portion between the first oxide portion and the silicon substrate by exposing the silicon substrate to an oxidizing ambient at a second temperature higher than the glass transition temperature for a second time period so that the second oxide portion has a thickness in a range of about 2 to 75% of a total thickness of the oxide layer. Also, respective contacts for the emitter, base and collector regions are formed.
The step of upwardly ramping may comprise upwardly ramping the temperature at a relatively high ramping rate to reduce any oxide formed during the upward ramping, and the relatively high ramping rate may be greater than about 35° C./minute. The step of growing the first oxide portion may further comprise exposing the silicon substrate to an oxidizing ambient containing a relatively small amount of oxygen during the upward ramping to reduce any oxide formed during upward ramping, and the relatively small amount of oxygen may be less than about 10%.
The step of upwardly ramping may comprise upwardly ramping at a relatively high rate and in an ambient so that an oxide thickness formed during the upward ramping is in a range of about 5 to 30% of the total thickness of the oxide layer. Also, the first temperature may be less than about 900° C., and the second temperature may be greater than about 925° C. Furthermore, the first temperature may be in a range of about 750° C. to 900° C., and the second temperature may be in a range of about 925° C. to 1100° C. The growing steps may be carried out in a single processing apparatus such as a furnace, a rapid thermal processor, or a fast thermal processor.
Objects, features and advantages in accordance with the present invention are also provided by a semiconductor device including a plurality of bipolar transistors formed on a silicon layer, wherein each bipolar transistor includes a graded, grown, oxide layer on the silicon layer and comprising a first portion and a second portion arranged in stacked relation with the second portion being adjacent the silicon layer and defining an interface therewith, the second portion having a thickness in a range of about 2 to 75% of a total thickness of the oxide layer, the silicon layer and the oxide layer being substantially stress-free adjacent the interface. Respective emitter, base and collector regions are in the silicon layer, and respective contacts for the emitter, base and collector regions are provided.
The interface may be substantially planar and may have a roughness of less than about 3 Angstroms. The silicon layer may comprise single crystal silicon and may be a silicon substrate.
REFERENCES:
patent: 4277320 (1981-07-01), Beguwala et al.
patent: 4518630 (1985-05-01), Grasser
patent: 4851370 (1989-07-01), Doklan e
Roy Kumar Pradip
Singh Ranbir
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Le Dung Anh
Lucent Technologies - Inc.
Nelms David
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