Method of making an interconnect structure with an integrated lo

Details Method of making an interconnect structure with an integrated lo Method of making an interconnect structure with an integrated lo

1994-05-20

1996-01-30

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437231, 437238, 437978, 148DIG43, 148DIG118, H01L 21441, H01L 21469

Patent

active

054880157

ABSTRACT:
This invention provides a semiconductor device and process for making the same with dramatically reduced capacitance between adjacent conductors and an interlayer dielectric construction which emphasizes mechanical strength, etch compatibility, and good heat transfer. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric and provide mechanical strength, heat transfer, and a solid layer for via etch. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

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