Method of making an integrated injection logic cell having self-

Details Method of making an integrated injection logic cell having self- Method of making an integrated injection logic cell having self-

1983-07-28

1985-04-23

Saba, William G.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29578, 29590, 29591, 148 15, 148175, 148188, 148190, 156643, 156653, 357 34, 357 35, 357 36, 357 46, 357 59, 357 92, H01L 21225, H01L 2131

Patent

active

045120757

ABSTRACT:
Base resistance in an integrated injection logic cell is reduced by providing a low resistance conductive path over the device cell and contacting the base regions of vertical transistors in the cell. In fabricating the I.sup.2 L cell a first intrinsic polysilicon layer is formed over the surface of the device cell, and N-type dopant is diffused through the polysilicon layer to form the N+ collectors of the NPN vertical transistors. Silicon oxide is formed over the doped polysilicon and the undoped intrinsic polysilicon is then removed. Exposed edge portions of the N doped polysilicon is then oxidized to completely insulate the surface of the polysilicon. A second layer of intrinsic polysilicon is then formed over the device cell and P type dopant is diffused through the second polysilicon layer to form the emitter and collector of a lateral PNP transistor and to contact the base regions of the NPN vertical transistors between the N+ collectors. The self-aligned collectors and bases of the NPN transistors and the reduced base resistance increases the speed of the I.sup.2 L device.

REFERENCES:
patent: 3962717 (1976-06-01), O'Brien
patent: 4148054 (1979-04-01), Hart et al.
patent: 4148055 (1979-04-01), Edlinger et al.
patent: 4160989 (1979-07-01), de Bribisson et al.
patent: 4190466 (1980-02-01), Bhattacharyya et al.
patent: 4322882 (1982-04-01), Vora
patent: 4338622 (1982-07-01), Feth et al.
Feth et al., "Layout Image for Merged-Transistor Logic", I.B.M. Tech. Discl. Bull., vol. 22, No. 7, Dec. 1979, pp. 2948-2951.
Hennig et al., IEEE J. of Solid State Circuits, vol. SC 12, No. 2, Apr. 1977, pp. 101-109.
Middelhoek et al., IEEE J. of Solid State Circuits, vol. SC 12, No. 2, Apr. 1977, pp. 135-138.
Mulder et al., IEEE J. of Solid State Circuits, vol. SC 11, No. 3, Jun. 1976, pp. 379-385.
Berger et al., IBM Tech. Discl. Bulletin, vol. 22, No. 7, Dec. 1979, pp. 2786-2788.
Tang et al., IEEE International Electron Dev. Meeting, Technical Digest, pp. 201-204, Dec. 2, 1979.
Berger et al., IBM Tech. Discl. Bulletin, vol. 21, No. 12, May 1979, p. 4886.
Jaeger et al., IBM Tech. Discl. Bulletin, vol. 19, No. 10, Mar. 1977, pp. 3942-3946.
Yeh, IBM Tech. Disclosure Bulletin, vol. 22, No. 9, Feb. 1980, pp.4047-4051.

Affiliated with

Also associated with

Rating

Method of making an integrated injection logic cell having self- does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making an integrated injection logic cell having self-, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making an integrated injection logic cell having self- will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-29882