Method of making an insulated gate field effect transistor by im

Details Method of making an insulated gate field effect transistor by im Method of making an insulated gate field effect transistor by im

1977-07-22

1978-08-22

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

357 23, 357 91, H01L 754, H01L 2978

Patent

active

041086864

ABSTRACT:
An insulated gate field effect transistor having spaced highly doped source and drain regions with less highly doped source and drain extensions, which define the ends of the channel of the transistor, has both the source and drain extensions and the channel of the transistor defined in a controllable manner by the steps of forming a continuous zone of the same conductivity type as the source and drain regions in the space between these two regions and then counterdoping a portion of this layer.

REFERENCES:
patent: 3387358 (1968-06-01), Heiman
patent: 3615934 (1971-10-01), Bower
patent: 3653978 (1972-04-01), Robinson et al.
patent: 3725136 (1973-04-01), Morgan
patent: 3814992 (1974-06-01), Kump et al.
patent: 4017888 (1977-04-01), Christie et al.
patent: 4021835 (1977-05-01), Etoh et al.
Moline et al., "Self-Aligned . . . Chan Stops . . . IGFET . . . ", IEEE, ED-20, (1973), 1129.
Fang et al., ". . . MOS. . . Using the Ion-Impln. . . . ", IEEE, vol. SC-10, No. 10, (1975), 265.
Runge, H., "Threshold Voltage . . . by Ion Impln.", Electr. Engr., Jan. 1976, p. 41.
Masuhara et al., ". . . MOSFET . . . by Ion Implantation", IEEE-Electron Device Meeting, 1974, p. 397.

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