Method of making an electrically erasable programmable memory de

Details Method of making an electrically erasable programmable memory de Method of making an electrically erasable programmable memory de

1994-05-06

1994-12-27

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 49, 437228, 257316, H01L 21265

Patent

active

053765729

ABSTRACT:
An improved structure and process of fabricating an electrically erasable programmable read only memory device (EEPROM's) wherein a thick oxide region is formed on the surface of a semiconductor substrate. The thick oxide is removed forming a depression in the surface. Impurity ions are implanted in the depression forming a highly doped tunneling region. A tunnel oxide layer is formed on the substrate surface fully covering the tunneling region. Next, the floating gate layer is formed on the tunnel oxide layer. The gate isolation layer and control gate layer are formed over the floating gate layer. Subsequently, the spaced source and drain regions are formed in the substrate on opposite sides of the gate structure. A dielectric layer is formed over the control gate region and substrate. Contact openings are formed. Electrical contacts and metallurgy lines with appropriate passivation are formed that connect the source, drain and gate elements to form an electrically erasable programmable read only memory device.

REFERENCES:
patent: 5108937 (1992-04-01), Tsai et al.
patent: 5180680 (1993-01-01), Yang
patent: 5273923 (1993-12-01), Chang et al.
patent: 5318921 (1994-06-01), Hsue et al.
"A Self Convergence Erasing Scheme For a Simple Stacked Gate Flash EEPROM", Yamada et al. IEDM '91 pp. 307-310 (1991).

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