Method of making an EEPROM with an erase gate

Details Method of making an EEPROM with an erase gate Method of making an EEPROM with an erase gate

1995-12-07

1997-07-01

Tsai, H. Jey

Fishing, trapping, and vermin destroying

437 52, 437203, 257320, H01L 218247

Patent

active

056438141

ABSTRACT:
A flash EEPROM cell structure and a method for forming it. The method of forming the EEPROM cell includes the steps of: forming a plurality of trenches on a substrate, the trenches being filled with an insulating layer; forming bit lines between the trenches and on the substrate; forming an insulating layer on the bit lines; forming a floating gate, with at least one side of it contacting with the bit lines; and simultaneously forming a control gate and an erasing gate. The control gate and the erasing gate cross the bit lines and the floating gate. The erasing gate also extends over the trenches. The floating gate and the erasing gate extend down into the trenches.

REFERENCES:
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patent: 4998220 (1991-03-01), Eitan et al.
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5380672 (1995-01-01), Yuan et al.
patent: 5460989 (1995-10-01), Wake
"A New Flash E.sup.2 PROM Cell Using Triple Polysilicon Technology," H. Masuoka, International Electron Devices Meeting 1984 Technical Digest, Dec. 1984, pp. 464-467.

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