Method of making an EEPROM cell with separate erasing and progra

Details Method of making an EEPROM cell with separate erasing and progra Method of making an EEPROM cell with separate erasing and progra

1994-12-23

1996-06-04

Fourson, George

Fishing, trapping, and vermin destroying

437 984, H01L 218247

Patent

active

055232493

ABSTRACT:
An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source region (11) and a drain region (12), with a corresponding channel region between. A Fowler-Nordheim tunnel-window (13a) is located over the source line (17) connected to source (11). A floating gate (13) includes a tunnel-window section. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the source (11) and drain (12) regions, such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch). The memory cell is programmed by hot-carrier injection from the channel to the floating gate (13), and erased by Fowler-Nordheim tunneling from the floating gate (13) through the tunnel window (13a) to the source-line (17 ). The program and erase regions of the cells are physically separate from each other, and the characteristics, including the oxides, of each of those regions may be made optimum independently from each other.

REFERENCES:
patent: 5008721 (1991-04-01), Gill et al.
patent: 5371031 (1994-12-01), Gill et al.
Kamins et al., "Device Electronics for Integrated Circuits", pp. 445-448, 1986, John Wiley & Sons.

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