Method of making a vertically formed neuron transistor having a

Details Method of making a vertically formed neuron transistor having a Method of making a vertically formed neuron transistor having a

1995-04-17

1996-01-02

Fourson, George

Fishing, trapping, and vermin destroying

437 52, 437915, 257316, H01L 218247

Patent

active

054808200

ABSTRACT:
A method for forming a vertical neuron MOSFET begins by providing a substrate (12). One or more conductive layers (24 and 28) are formed overlying the substrate (12). An opening (32) is formed through a portion of the conductive layers (24 and 28) to form one or more control electrodes from the conductive layers (24 and 28). A floating gate (36, and 38) is formed adjacent each of the control electrodes. A dielectric layer (34) is formed within the opening (32) and between the control electrodes and the floating gate (36, and 38) to provide for capacitive coupling between the control electrodes and the floating gate (36, and 38). The capacitive coupling may be altered for each control electrode via isotropic sidewall etching and other methods. By forming the neuron MOSFET in a vertical manner, a surface area of the neuron MOSFET is reduced when compared to known neuron MOSFET structures.

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"An Intelligent MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations," by Tadashi Shibata and Tadahiro Ohmi, 1991 IEDM, pp. 919-922.

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