Method of making a V-MOS field effect transistor for a dynamic m

Details Method of making a V-MOS field effect transistor for a dynamic m Method of making a V-MOS field effect transistor for a dynamic m

1977-12-27

1978-09-26

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

148187, 357 23, 357 50, 357 91, H01L 2704, H01L 2978, H01L 21265

Patent

active

041167201

ABSTRACT:
This disclosure relates to a method of making a V-MOS field effect transistor which does not require the extra steps of epitaxial growth in order to form the source area of the transistor. The formation of the source area is achieved by masking the silicon substrate, opening an aperture in the mask and then etching the silicon substrate in such a manner as to undercut the mask so that the mask provides a shield to subsequent ion implanting of the source area. Both P and N type dopants can be separately implanted with different energy levels so as to form an enhanced PN junction capacitance for the device. Such a field effect transistor can be achieved without the formation of a graded dopant concentration in the channel between the source and drain areas of the transistor and is provided with enhanced source capacitance.

REFERENCES:
patent: 3901737 (1975-08-01), Dash
patent: 3920482 (1975-11-01), Russell
patent: 3924265 (1975-12-01), Rodgers
patent: 3986200 (1976-10-01), Allison
patent: 4003036 (1977-01-01), Jenne
patent: 4003126 (1977-01-01), Holmes et al.
patent: 4037306 (1977-07-01), Gutteridge et al.
patent: 4047195 (1977-09-01), Allison
patent: 4047975 (1977-09-01), Widman
patent: 4048649 (1977-09-01), Bohn
patent: 4065783 (1977-12-01), Ouyang

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