Method of making a through hole in multi-layer insulating films

Details Method of making a through hole in multi-layer insulating films Method of making a through hole in multi-layer insulating films

1991-04-03

1995-01-03

Hille, Rolf

Fishing, trapping, and vermin destroying

437190, 437 89, 257637, 257740, 257774, H01L 2954, H01L 2120

Patent

active

053786521

ABSTRACT:
A semiconductor device with an electrode wiring structure comprises at least one diffused region provided in a semiconductor substrate, a silicon oxide layer covering the substrate surface, a silicon nitride layer provided on the silicon oxide layer, a through-hole reaching the diffused region through the silicon oxide layer from an upper surface of the silicon nitride layer, a silicon semiconductor layer filled in the through-hole and serving as an electrode wiring layer, and an interconnection layer electrically connected to the diffused region through the silicon semiconductor layer. According to the structure, since the silicon oxide layer is covered with the silicon nitride layer, unwanted contaminations such as phosphorus, boron, etc., previously contained in the silicon oxide layer are not added to the silicon semiconductor layer during its growth process. Therefore, the electrode wiring layer of silicon semiconductor having controlled conductivity can be provided.

REFERENCES:
patent: 4884123 (1989-11-01), Dixit et al.
patent: 5116780 (1992-05-01), Samata et al.
Wolf et al, "Silicon Processing For VLSI ERA", Lattice Press, Sunset Beach, Calif. 1986 pp. 182-191.
"The Selective Epitaxial Growth of Si by using Silicon Nitride Film as a Mask", Ogawa et al, Jap. J. Appl. Phys., vol. 10, #12, Dec. 1971, pp. 1675-1679.
"Selective Si Epitaxy Using Reduced Pressure Technique", Tanno et al, Jap. J. Appl. Phys., vol. 21, #9, Sep. 1982, pp. L564-L566.
"Novel Device Structures by Selective Epitaxial Growth (SEG)", Borland, IEDM 1987, pp. 12-15.
"Novel Selective Poly-and Epitaxial-Silicon Growth (SPEG) Technique For VLSI Processing", Mieno et al, IEDM 1987, pp. 16-19.
Shibata, H., et al., "Low Resistive and Selective Silicon Growth as a Self-Aligned Contact Hole Filler and its Application to a 1M bit State Ram", Technical Digest for 1987 Symposium on VLSI Technology, pp. 75-76, published 1984.

Affiliated with

Also associated with

Rating

Method of making a through hole in multi-layer insulating films does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making a through hole in multi-layer insulating films, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making a through hole in multi-layer insulating films will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2211299