Method of making a three dimensional trench EEPROM cell structur

Details Method of making a three dimensional trench EEPROM cell structur Method of making a three dimensional trench EEPROM cell structur

1994-05-17

1996-10-22

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 67, 437915, H01L 218247

Patent

active

055676359

ABSTRACT:
The objects of the present invention are accomplished by merging a MOS-FET device and a floating gate into a three dimensional trench structure. The trench device cell has four vertical sides and bottom. The bottom of the trench forms the channel region of the transfer FET of the EEPROM cell. The heavily doped source and drain regions are formed on two vertical sidewalls of the trench and oppositely face each other. The heavily doped regions cover the entire sidewall and have a depth which is greater than the trench depth so that the channel region is defined by the bottom of the trench. The remaining two vertical sidewalls of the trench are formed by isolation oxide. A first silicon dioxide layer covers the bottom of the trench and forms part of the gate oxide of the cell device. A second silicon dioxide layer covers the vertical sidewalls of the trench. The second silicon dioxide layer is relatively thin with respect to the gate oxide layer. The second silicon dioxide layer separates the source and drain regions from the floating gate which overlays both the first and second silicon dioxide layers. The floating gate overlaps all four trench sidewalls and substantially increases the coupling between the floating-gate and the control-gate.

REFERENCES:
patent: 4796228 (1989-01-01), Baglee
patent: 4979004 (1990-12-01), Esquivel et al.
patent: 4990979 (1991-02-01), Otto
patent: 5180680 (1993-01-01), Yang
European Search Report Dated Jul. 21, 1994.

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