Method of making a thin film transistor structure with improved

Details Method of making a thin film transistor structure with improved Method of making a thin film transistor structure with improved

1992-11-18

1994-11-08

Thomas, Tom

Fishing, trapping, and vermin destroying

437192, 437981, H01L 21265

Patent

active

053626605

ABSTRACT:
Minimum line spacing is reduced and line spacing uniformity is increased in thin film transistors by employing source/drain metallization having a first relatively thin layer of a first conductor and a second relatively thick layer of a second conductor. The second conductor is selected to be one which may be preferentially etched in the presence of the first conductor whereby the first conductor acts as an etch stop for the etchant used to pattern the second conductor portion of the source/drain metallization. This etching is preferably done using dry etching. Dry etching typically provides substantially better control of line width than wet etching. The etching of the second conductor can be done with a dry etch process which etches the photoresist at substantially the same rate as the second conductor whereby the second conductor is provided with a sidewall slope of substantially 45.degree. which improves the quality of passivation provided by subsequent deposition of a conformal passivating layer.

REFERENCES:
patent: 4651185 (1987-03-01), Holmberg et al.
patent: 4700458 (1987-10-01), Suzuki et al.
patent: 4736229 (1988-04-01), Holmberg et al.
patent: 4778560 (1988-10-01), Takeda et al.
patent: 4889983 (1989-12-01), Numano et al.
patent: 4918494 (1990-04-01), Koden et al.
patent: 5028551 (1991-07-01), Dohjo et al.
patent: 5061648 (1991-10-01), Aoki et al.
B. Gorowitz, R. J. Saia, E. W. Balch, "Methods of Metal Patterning and Etching for VLSI" General Electric Co. Technical Information Series, Mar. 1987; See pp. 22-25, also published in VLSI Electronics Microstructure Science (N. Einspruch, S. Cohen, G. Gildenblat, Eds.) vol. 15, Chap. 4, p. 159(1987).
R. J. Saia, B. Gorowtiz, "The Reactive Ion Etching of Molybdenum and Bilayer Metallization Systems Containing Molybdenum," Journal of the Elctrochemical Society, vol. 135, pp. 2795-2802 (Nov. 1988) (See p. 2797 for discussion of one step MO-CR etching).
Y. Kuo, J. Crowe, "Slope Control of Molybdenum Lines Etched With Reactive Ion Etching," J. Vac. Sci. Technical, pp. 1529-1532 (May/Jun. 1990) (See p. 1529 for discussion of MO etching).
R. Kwasnick, G. Possin, R. Saia, "Reactive Ion Etched MO/CR Source-Drain Metallization For Amorphous Silicon Thin Film Transistors," Materials Res. Soc, Symposium Proc. Apr. 1991.

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