Method of making a sub-micron NMOS, PMOS and CMOS devices with m

Details Method of making a sub-micron NMOS, PMOS and CMOS devices with m Method of making a sub-micron NMOS, PMOS and CMOS devices with m

1990-05-30

1992-05-19

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 34, 437 41, 437186, 437193, 148DIG20, 357 34, H01L 2170

Patent

active

051148749

ABSTRACT:
The sub-micron NMOS, PMOS and CMOS devices with methods for forming sub-micron contacts provide sub-micron devices and processes for manufacturing them with contacts down to 0.1 microns or less. All processes and devices utilize doped polysilicon as the electrodes for the device elements, and the preferred embodiment surrounds the polysilicon contacts with low temperature oxide covered by SOG which avoids all oxidation steps that could be detrimental in this contact size range. An optional alternative includes large contact area enlarging layers of silicide directly beneath each contact.

REFERENCES:
patent: 4494304 (1985-01-01), Yoshioka
patent: 4694565 (1987-09-01), Custode
patent: 4697328 (1987-10-01), Custode
patent: 4868137 (1989-09-01), Kubota
patent: 4945070 (1990-07-01), Hsu
patent: 4947225 (1990-08-01), Custode
patent: 4957881 (1990-09-01), Crotti

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