Method of making a stacked copacitor for DRAM cell

Details Method of making a stacked copacitor for DRAM cell Method of making a stacked copacitor for DRAM cell

1989-11-30

1992-05-26

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 47, 437 60, 437233, 437235, 437919, H01L 2170, H01L 27108

Patent

active

051167760

ABSTRACT:
A capacitor suitable for use with a DRAM memory cell is composed of multiple layers of polycrystalline silicon. The storage node is formed from a polycrystalline silicon layer sandwiched between two polysilicon ground plate layers. Such a structure nearly doubles the capacitance for a given chip surface area used. First the bottom polycrystalline silicon plate layer is fabricated, followed by an isolation step and fabrication of the storage node polycrystalline silicon layer. Following another isolation step, the polycrystalline silicon top plate layer is then formed and connected to the bottom plate layer.

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Stacked Capacitor Cells for High-Denisty Dynamic Rams, Hidehiro Watanabe, et al. 1988 IDEM Conference Proceedings, pp. 600-603.

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