Method of making a split floating gate EEPROM cell

Details Method of making a split floating gate EEPROM cell Method of making a split floating gate EEPROM cell

1992-08-14

1994-02-08

Fourson, George

Fishing, trapping, and vermin destroying

437978, 437979, 257321, H01L 21336

Patent

active

052847861

ABSTRACT:
A split floating gate EEPROM memory cell formed in a P-type silicon substrate includes source and drain buried n+ diffusion regions formed in the silicon substrate to define a substrate channel region therebetween. A layer of floating gate oxide about 400.ANG. thick is formed over the source and drain regions and over the channel region. The floating gate oxide includes a region of thin tunnel oxide about 80-100.ANG. thick formed therein over the drain region. A floating gate is formed on the floating gate oxide to extend over the channel region and includes a portion that extends over the tunnel oxide. The floating gate comprises a first layer of polysilicon about 300-600.ANG. thick, a silicon dioxide layer about 20-50.ANG. thick formed on the first layer of polysilicon, and a second layer of polysilicon about 2000.ANG. thick formed on the silicon dioxide layer. A layer of ONO is formed on the floating gate and a polysilicon control gate is formed on the layer of ONO.

REFERENCES:
patent: 4992391 (1991-02-01), Wang
patent: 5049516 (1991-09-01), Arima

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