Method of making a single transistor non-volatile electrically a

Details Method of making a single transistor non-volatile electrically a Method of making a single transistor non-volatile electrically a

1992-10-15

1994-01-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437242, 437983, 148DIG1, 148DIG112, H01L 21266

Patent

active

052780872

ABSTRACT:
A single transistor electrically programmable and erasable memory cell has a substrate of a semiconductor material of a first-conductivity type. Within the substrate are defined source, drain, regions with a channel region therebetween. A first insulating layer is disposed over the substrate and over the source, channel and drain regions. An electrically conductive, re-crystallized floating gate is disposed over the first-insulating layer and extends over a portion of the channel region and over a portion of the drain region to maximize capacitive coupling therewith. A second insulating layer has a top wall portion over the floating gate and a side wall portion immediately adjacent to the floating gate and has a thickness which permits the Fowler-Nordheim tunneling of charges therethrough. An electrically conductive control gate has two electrically connected sections: A first section is over the first insulating layer and is immediately adjacent to the side-wall portion of the second insulating layer. The first section extends over a portion of the channel region and over the source region. A second section is disposed over the top wall portion of the second insulating layer to minimize capacitive coupling with the floating gate.

REFERENCES:
patent: 4203158 (1980-05-01), Frohman-Bentchkowsky
patent: 4274012 (1981-06-01), Simko
patent: 4462089 (1984-07-01), Miida et al.
patent: 4599706 (1986-07-01), Guterman
patent: 4619034 (1986-10-01), Janning
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 4964143 (1990-10-01), Haskell
patent: 5017505 (1991-05-01), Fujii et al.
patent: 5045488 (1991-09-01), Yeh
"Electron Tunneling in Non-Planar Floating Gate Memory Structure", by R. K. Ellis et al., IEEE, May 1989, pp. 749-752.
"A New NMOS Charge Storage Effect", by H. G. Dill et al., Solid State Electronics, 1969, vol. 12, pp. 981-987.

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