Method of making a shallow trench isolation for ULSI formation v

Details Method of making a shallow trench isolation for ULSI formation v Method of making a shallow trench isolation for ULSI formation v

1998-04-21

2000-05-02

Dang, Trung

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438424, 438435, 438437, 148DIG50, H01L 2176

Patent

active

060572108

ABSTRACT:
A silicon dioxide layer and a silicon nitride layer are formed on the wafer. Subsequently, a plurality of shallow trenches are generated in the wafer. A HDP-CVD oxide having protruding portions is refilled into the trenches and formed on the silicon nitride layer for isolation. A wet etch is performed to etch the HDP-CVD oxide layer such that the corners of the silicon nitride layer formed on the active area will be exposed. A cap silicon nitride layer is then conformally formed on the surface of the oxide layer. Then, a chemical mechanical polishing (CMP) process is used to remove the top of the cap silicon nitride layer, thereby exposing the residual protruding portions of the oxide layer. The residual protruding portions of the oxide layer are next removed. Then, the silicon nitride layer and the cap silicon nitride layer are both removed by conventional methods. Finally, the pad oxide is removed.

REFERENCES:
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patent: 5851899 (1998-12-01), Weigand
patent: 5880007 (1999-03-01), Varian et al.
Chatterjee, A. et al., "Intergration of unit proceses in a shallow trench isolation module for a 0.25 .mu.m complementary metal-oxide semiconductor technology," J. Vac.Sci.Technol. B. 15(6), Nov./Dec. 1997, pp. 1936-1942.

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