Method of making a semiconductor memory device

Details Method of making a semiconductor memory device Method of making a semiconductor memory device

1988-08-26

1990-03-20

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437 52, 437 60, 437919, H01L 2172

Patent

active

049101617

ABSTRACT:
A semiconductor memory comprises a p.sup.- -type semiconductor substrate (1), a p-type epitaxial layer (15) and p.sup.+ -type epitaxial layers (16, 17) formed thereon, an n.sup.+ -type region (6) formed on the p.sup.+ -type epitaxial layer (16) to serve as a bit line, an n.sup.+ -type region (5) formed on the p.sup.+ -type epitaxial layer (17) to serve as a charge storage region and a gate electrode (9) formed on the p-type epitaxial layer (15) to serve as a word line. The p.sup.+ -type epitaxial layers (16, 17) prevent passage of electrons within electron-hole pairs induced by alpha rays, to suppress occurrence of soft errors. The p-type epitaxial layer (15) defines a region corresponding to the channel region of a bus transistor, whereby the impurity concentration thereof can be easily controlled, to readily set the threshold voltage of the bus transistor at an appropriate level.

REFERENCES:
patent: 4328611 (1980-04-01), Harrington
patent: 4688064 (1987-08-01), Oaura
"Building a Dynamic RAM with SMOS", Electronic Design, Mar. 18, 1982, p. 233. IBM Technical Disclosure Bulletin, vol. 26, No. 3A, Aug. 1983, pp. 940-942, New York, G. A. Sai-Halasz et al.: Bipolar Dynamic RAM Cell Structure with Low Soft-Error Rate.

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